Diode structure and method for gate all around silicon nanowire technologies
US8927397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.