Diode structure and method for FINFET technologies
US8928083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.