Low latency concurrent computation
US8928677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.