Receiver with enhanced clock and data recovery
US8929496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2009 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.