Relaxed coherency between different caches
US8930636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.