Reconfigurable processor and method for processing a nested loop
US8930929B2 · kind B2 · utility
1Cited by
12References
19Claims
0Family size
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Key dates
| Filing date | Apr 14, 2011 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.