Split-gate non-volatile memory (NVM) cell and device structure integration
US8932925B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.