Triple patterning NAND flash memory with SOC
US8932955B1 · kind B1 · utility
11Cited by
10References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.