3D non-volatile memory with metal silicide interconnect
US8933502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2011 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Nov 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.