Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis
US8934377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Jul 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/2408
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.