System and method for performing scan test
US8935584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Apr 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.