Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

US8936977B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Jan Hoentschel · Dresden, DE
• Shiang Yang Ong · Singapore, SG
• Stefan Flachowsky · Dresden, DE
• Thilo Scheiper · Dresden, DE

Key dates

• Filing date: May 29, 2012
• Grant date: Jan 20, 2015
• Expiry date: May 29, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.