Method and apparatus for comprehension of common path pessimism during timing model extraction
US8938703B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2014 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Jul 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs that are necessary for the identification and removal of common path pessimism, the timing information of the topologically crucial points of the design block will be retained in the ETM, and the non-essential and noisy information will be removed from the ETM to ensure that the ETM is robust and compact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.