Method for forming through silicon via with wafer backside protection
US8940637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/1357
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.