Substrate wiring method and semiconductor manufacturing device
US8940638B2 · kind B2 · utility
4Cited by
1References
12Claims
0Family size
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Key dates
| Filing date | Feb 23, 2011 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | May 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.