Erasable programmable single-ploy nonvolatile memory
US8941167B2 · kind B2 · utility
16Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Mar 8, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | May 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.