Semiconductor devices having different gate oxide thicknesses
US8941177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Feb 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.