Electronic component package fabrication method and structure
US8941250B1 · kind B1 · utility
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165References
20Claims
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Key dates
| Filing date | Feb 17, 2014 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Feb 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.