Storing branch information in an address table of a processor
US8943301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2011 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Nov 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.