Method and apparatus for synthesising a sum of addends operation and an integrated circuit
US8943447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for a synthesizing In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimization constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesized in RTL (31) before manufacturing an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.