Packet assembly module for multi-core, multi-thread network processors
US8943507B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Oct 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.