Patent · US Active

Method of making a vertical NAND device using sequential etching of multilayer stacks

US8946023B2 · kind B2 · utility

87Cited by
16References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 2, 2013
Grant dateFeb 3, 2015
Priority date
Expiry dateJul 2, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/10

Abstract

A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.