Power/ground layout for chips
US8946890B2 · kind B2 · utility
2Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2011 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Apr 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.