Patent · US Active

Shared integrated sleep mode regulator for SRAM memory

US8947967B2 · kind B2 · utility

2Cited by

0References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Michael A. Dreesen · Austin, US
Stephen Greenwood · Fort Collins, US
Bruce A. Doyle · Longmont, US

Key dates

Filing date	Dec 21, 2012
Grant date	Feb 3, 2015
Priority date	—
Expiry date	Jul 30, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.