Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage
US8947970B2 · kind B2 · utility
11Cited by
8References
19Claims
0Family size
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Key dates
| Filing date | Jul 13, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Jan 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.