Method for fabricating passive devices for 3D non-volatile memory
US8951859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2011 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.