DRAM cell design with folded digitline sense amplifier
US8952437B2 · kind B2 · utility
2Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 2014 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | May 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.