Dynamic bit line bias for programming non-volatile memory
US8953386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2012 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jun 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.