Structured placement of latches/flip-flops to minimize clock power in high-performance designs

US8954912B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Charles J. Alpert · Cedar Park, US
• Zhuo Li · Austin, US
• Gi-Joon Nam · Austin, US
• Shyam Ramji · Lagrangeville, US
• Chin Ngai Sze · Austin, US
• Paul G. Villarrubia · Austin, US
• Natarajan Viswanathan · Austin, US

Key dates

• Filing date: Nov 29, 2012
• Grant date: Feb 10, 2015
• Expiry date: Nov 29, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/392
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.