Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit
US8954915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | May 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.