Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
US8956889B2 · kind B2 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Aug 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.