Method for stress reduced manufacturing semiconductor devices

US8956960B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Irsigler · Ried im Innkreis, AT
• Hans-Joachim Schulze · Taufkirchen, DE

Key dates

• Filing date: Nov 16, 2012
• Grant date: Feb 17, 2015
• Expiry date: Feb 1, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H29/14
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.