Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity
US8957531B2 · kind B2 · utility
2Cited by
14References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2011 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.