Partitioned erase and erase verification in non-volatile memory
US8958249B2 · kind B2 · utility
10Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2014 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Mar 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.