Three-dimensional integrated circuit device using a wafer scale membrane
US8963278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Nov 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.