James Vichiconti
14Patents
4h-index
40Co-inventors
56Inventor score
Filing activity: Nov 10, 1998 → Aug 4, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6209575A | Tamper proof set screw | Emerging Cross-Sectional Technologies | 18 | Expired |
| US9431487B2 | Graphene layer transfer | Electricity | 6 | Active |
| US7528056B2 | Low-cost strained SOI substrate for high-performance CMOS technology | Electricity | 5 | Active |
| US6928380B2 | Thermal measurements of electronic devices during operation | Physics | 5 | Expired |
| US8878259B2 | Super lattice/quantum well nanowires | Electricity | 4 | Active |
| US7935612B1 | Layer transfer using boron-doped SiGe layer | Electricity | 4 | Active |
| US8273591B2 | Super lattice/quantum well nanowires | Electricity | 3 | Active |
| US8232171B2 | Structure with isotropic silicon recess profile in nanoscale dimensions | Emerging Cross-Sectional Technologies | 1 | Active |
| US8440494B2 | Single-crystalline silicon alkaline texturing with glycerol or ethylene glycol additives | Emerging Cross-Sectional Technologies | 0 | Active |
| US9412620B2 | Three-dimensional integrated circuit device fabrication including wafer scale membrane | Electricity | 0 | Active |
| US8081280B2 | Method of producing UV stable liquid crystal alignment | Physics | 0 | Active |
| US8963278B2 | Three-dimensional integrated circuit device using a wafer scale membrane | Electricity | 0 | Active |
| US8637953B2 | Wafer scale membrane for three-dimensional integrated circuit device fabrication | Electricity | 0 | Active |
| US9859379B2 | Graphene layer transfer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.