SRAM layouts
US8964453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.