Vector width-aware synchronization-elision for vector processors
US8966461B2 · kind B2 · utility
4Cited by
7References
16Claims
0Family size
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Key dates
| Filing date | Sep 29, 2011 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.