Method for producing a transistor structure with superimposed nanowires and with a surrounding gate
US8969148B2 · kind B2 · utility
15Cited by
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10Claims
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Key dates
| Filing date | Apr 15, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Apr 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.