Method and system for a GaN vertical JFET utilizing a regrown channel

US8969912B2 · kind B2 · utility

Assignee

• Avogy, Inc. · US

Inventors

• Isik C. Kizilyalli · San Francisco, US
• Hui Nie · Cupertino, US
• Andrew P. Edwards · San Jose, US
• Linda Romano · Sunnyvale, US
• David P. Bour · Cupertino, US
• Richard J. Brown · Los Gatos, US
• Thomas R. Prunty · Santa Clara, US

Key dates

• Filing date: Aug 4, 2011
• Grant date: Mar 3, 2015
• Expiry date: Sep 3, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.