Transistor-based apparatuses, systems and methods
US8969924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.