Patent · US Active

Low latency two-level interrupt controller interface to multi-threaded processor

US8972642B2 · kind B2 · utility

4Cited by

18References

29Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Suresh K. Venkumahanti · Austin, US
Lucian Codrescu · Austin, US
Erich James Plondke · Austin, US
Xufeng Chen · San Diego, US
Peixin Zhong · San Diego, US

Key dates

Filing date	Oct 4, 2011
Grant date	Mar 3, 2015
Priority date	—
Expiry date	Mar 24, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/24
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.