TFT with insert in passivation layer or etch stop layer

US8975625B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Yan Ye · Saratoga, US
• Harvey YOU · Mountain View, US

Key dates

• Filing date: Jul 1, 2013
• Grant date: Mar 10, 2015
• Expiry date: Jul 1, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/80

Abstract

Embodiments disclosed herein generally relate to thin film transistors with one or more trenches to control the threshold voltage and off-current and methods of making the same. In one embodiment, a semiconductor device can include a substrate comprising a surface with a thin film transistor formed thereon, a first passivation layer formed over the thin film transistor, a trench formed within the first passivation layer and a second passivation layer formed over the first passivation layer and within the trench.