Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

US8975704B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Jan Hoentschel · Dresden, DE
• Shiang Yang Ong · Singapore, SG
• Stefan Flachowsky · Dresden, DE
• Thilo Scheiper · Dresden, DE

Key dates

• Filing date: Mar 4, 2014
• Grant date: Mar 10, 2015
• Expiry date: Mar 4, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693

Abstract

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.