Gate stacks including TaXSiYO for MOSFETS
US8975706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/08
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.