Inventor · Anaheim, CA, US

Khaled Ahmed

29Patents
8h-index
42Co-inventors
75Inventor score

Filing activity: Jun 5, 2000 → Jul 26, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US7910446B2 Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices Electricity 40 Active
US8043907B2 Atomic layer deposition processes for non-volatile memory devices Electricity 38 Active
US9246013B2 IGZO devices with composite channel layers and methods for forming the same Electricity 21 Active
US6472233B1 MOSFET test structure for capacitance-voltage measurements Electricity 20 Expired
US7659158B2 Atomic layer deposition processes for non-volatile memory devices Electricity 18 Active
US7078302B2 Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal Electricity 17 Expired
US9082793B1 IGZO devices with reduced threshhold voltage shift and methods for forming the same Electricity 12 Active
US7902018B2 Fluorine plasma treatment of high-k gate stack for defect passivation Electricity 8 Active
US7727828B2 Method for fabricating a gate dielectric of a field effect transistor Electricity 7 Active
US7871942B2 Methods for manufacturing high dielectric constant film Electricity 6 Active
US7888217B2 Method for fabricating a gate dielectric of a field effect transistor Emerging Cross-Sectional Technologies 5 Active
US9722049B2 Methods for forming crystalline IGZO with a seed layer Electricity 3 Active
US7611976B2 Gate electrode dopant activation method for semiconductor manufacturing Electricity 3 Active
US8993058B2 Methods and apparatus for forming tantalum silicate layers on germanium or III-V semiconductor devices Electricity 2 Active
US9076641B2 Ultra-low resistivity contacts Electricity 2 Active
US9076651B1 Gate stacks and ohmic contacts for SiC devices Electricity 1 Active
US9177791B2 Systems and methods for forming semiconductor devices Electricity 1 Active
US9093264B2 Methods and apparatus for forming silicon passivation layers on germanium or III-V semiconductor devices Electricity 1 Active
US9441298B2 Devices including metal-silicon contacts using indium arsenide films and apparatus and methods Electricity 0 Active
US8906709B1 Combinatorially variable etching of stacks including two dissimilar materials for etch pit density inspection Electricity 0 Active
US9373516B2 Method and apparatus for forming gate stack on Si, SiGe or Ge channels Electricity 0 Active
US12119367B2 Composite substrate for fabricating III-V photodetector arrays Electricity 0 Active
US9082729B2 Combinatorial method for solid source doping process development Electricity 0 Active
US9190320B2 Devices including metal-silicon contacts using indium arsenide films and apparatus and methods Electricity 0 Active
US8975706B2 Gate stacks including TaXSiYO for MOSFETS Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.