Semiconductor device with reduced contact resistance and method of manufacturing thereof
US8975708B2 · kind B2 · utility
5Cited by
25References
18Claims
0Family size
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Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.