Patent · US Active

Multiple depth vias in an integrated circuit

US8980723B2 · kind B2 · utility

1Cited by
0References
7Claims
0Family size

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Inventors

Key dates

Filing dateJun 14, 2013
Grant dateMar 17, 2015
Priority date—
Expiry dateSep 25, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.