Adhesion layer for through silicon via metallization
US8980746B2 · kind B2 · utility
3Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Sep 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming copper filled through silicon via features in a silicon wafer is provided. Through silicon vias are etched in the wafer. An insulation layer is formed within the through silicon vias. A barrier layer is formed within the through silicon vias. An oxide free silicon, germanium, or SiGe adhesion layer is deposited over the barrier layer. A seed layer is deposited over the adhesion layer then the wafers is annealed. The features are filled with copper or copper alloy. The stack is annealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.