Semiconductor package structure
US8981575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.